1. Field of the Invention
The present invention relates to the memory field. More specifically, the present invention relates to the reading of memory devices.
2. Description of the Related Art
Memory devices are commonly used to store information (either temporarily or permanently) in a number of applications; for example, in a non-volatile memory device the information is preserved even when a power supply is off. Typically, the memory device includes a matrix of memory cells (for example, consisting of floating gate MOS transistors); each memory cell has a threshold voltage that can be programmed to different levels representing corresponding logical values. Particularly, in a multi-level memory device each cell can take more than two levels (and then store a plurality of bits).
The logical values stored in selected cells of the memory device are read by comparing a current flowing through each memory cell with the currents provided by reference cells having predefined threshold voltages. For this purpose, a suitable biasing voltage is applied to the selected memory cells and to the reference cells.
A particular reading technique is disclosed in US2004/0257876 (the entire disclosure of which is herein incorporated by reference). This document proposes the use of a biasing voltage having a ramp-like time pattern. In this case, the selected memory cells and the reference cells turn on at different times (as soon as the biasing voltage reaches their threshold voltages). The temporal order of the turning on of each memory cell with respect to the ones of the reference cells uniquely identifies the logical value stored therein. In this way, the precision of the reading operation is strongly improved and made independent of most external factors.
Similar considerations apply to a program-verify operation, wherein each selected memory cell is compared with a further reference cell having a threshold voltage slightly higher than the one corresponding to the target logical value (so as to ensure that the memory cell has been brought to the desired condition). A further reference cell (with a threshold voltage slightly lower than the one corresponding to an erased condition) is used during an erase-verify operation to determine whether all the memory cells have been successfully erased. Likewise, a still further reference cell (with a threshold voltage still lower than the one corresponding to the erased condition) is used during a depletion-verify operation to identify any depleted memory cells that have been over-erased to a too low threshold voltage. Moreover, additional reference cells with threshold voltages between the ones of the different logical values and the ones of the corresponding program-verify levels are used during a refresh operation (to restore the correct condition of any memory cells that are drifting towards a lower logical value).
A problem of the memory devices known in the art is the correct setting of the several reference cells. Indeed, the difference between the threshold voltages of each pair of adjacent reference cells must be maintained at a predefined value with a very high accuracy, since any drift reduces a window that is available to discriminate the corresponding conditions of the selected memory cells. This problem is particularly acute for each reference cell used during the read operation and the corresponding reference cell(s) used for reading the selected memory cells with a margin (for example, during the program-verify operation or the refresh operation); indeed, in this case the difference between their threshold voltages is very low (for example, of the order of 50-150 mV).
Therefore, the setting of the reference cells requires a very accurate trimming of the desired threshold voltages. This involves a long test time of the memory device, for example, during an electrical wafer sorting (EWS) process. All of the above has a detrimental impact on the production time of the memory device, and then on its cost.